Job Information
Nvidia Senior ASIC Engineer in Shanghai, China
We are looking for a system-level ASIC design engineer for the PMU and SECIP team. Our team owns three critical GPU IPs — PMU (GPU Power Management), GSP (GPU Service Processor), and SEC (GPU Security Engine) — each of which instantiates a RISC-V-based subsystem called Peregrine, developed by a neighboring team. As GPU systems grow increasingly complex and software teams continue to push more workloads onto these engines, we need a system-level ASIC engineer to help gather Peregrine configuration requirements for all three engines and drive the integration of the Peregrine IP into each of them.
What You'll Be Doing:
Analyze architectural requirements to define the Peregrine configuration for PMU, GSP, and SEC engines, including how each integrates into the GPU chip.
Develop essential wrapper logic as needed to bridge the Peregrine subsystem with each engine's interfaces.
Drive the SOCD effort to integrate Peregrine into GPU engines, from RTL through synthesis handoff.
Collaborate with the Physical Design team on partition assignment and floorplan considerations.
Work with software teams to evaluate system-level performance — particularly memory access latency and bandwidth — ensuring it meets firmware requirements.
What We Need to See:
BS or MS in Electrical Engineering or Computer Engineering. MS preferred.
3+ years of relevant work experience.
Strong communication skills, as this role requires frequent collaboration across multiple teams (architecture, software, physical design, and IP).
Solid foundation in front-end ASIC design (RTL coding, synthesis, lint/CDC).
Self-motivated with excellent analytical and problem-solving skills.
Ways to Stand Out from the Crowd:
Experience in system-level chip integration or SoC-level design.
Familiarity with RISC-V processor subsystems or embedded firmware workflows.
Prior exposure to multi-die / chiplet architectures.