Job Information
Teradyne Senior Logic Design Manager (Teradyne, North Reading) in North Reading, Massachusetts
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne (http://www.teradyne.com/) companies deliver manufacturing automation across industries and applications around the world!
We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.
Our Purpose
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.
Opportunity Overview
The Teradyne Compute Test Division Engineering team is seeking a Senior manager to lead our FPGA design and verification team. Development occurs in a dynamic and challenging multi-site environment. The ideal candidate will have a passion for working with hardware and software subject matter experts to make complex hardware and software come together into a working system.
Oversee the Compute Test Division FPGA Design and Verification teams (25 full time resources and about as many contractors)
Direct line management of the FPGA design and verification staff 2-3 mgrs and 2-3 senior technical leads
Maintain/improve FPGA design and verification process/tools.
Manage FPGA team work force plan/staffing.
Collaborate with other Logic Design and embedded firmware(LDE) teams/managers (Embedded Firmware and HAL) to staff and execute projects.
Collaborate with Hardware, Software and Systems engineering to develop high quality semiconductor test instruments.
Work with the tools and technology group to manage the relationship with EDA tools vendors.
Work with the supply business management team to manage the relationship with FPGA vendors.
Hands-on FPGA architecture, implementation, testing and product integration debug as required.
May at times require FPGA project management including:
Project planningSchedule/budget tracking
Resource management including contractors on and offshore
Status reporting to management
Technical oversight: doc/code reviews, bug tracking
All About You
We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.
Minimum of 10 years of FPGA/ASIC design experience.
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation, lab validation to production release.
3-5 years of experience as a first level manager of an engineering team.
Extensive experience coding RTL (Verilog preferred).
Extensive experience using digital simulation tools (Cadence preferred).
Extensive experience using static timing analysis tools.
Experience designing with the following: PCIe, DDR3/4, AXI, ethernet, SPI, SERDES
Experience using digital design quality tools e.g. LINT, CDC, LEC.
Experience with either AMD or Altera FPGAs and development tools, preferably both.
Experience with bug tracking tools (Jira etc.)
Experience with source control systems (Clearcase, Git, CVS) and continuous integration.
Familiarity with digital verification tools and methodologies (preferably UVM).
Experience with project scheduling tools (e.g. Microsoft project)
Experience with embedded processors and digital signal processing is a plus.
Experience with high level programming languages (C, C++) is a plus.
Experience developing hardware for automated test equipment is a plus.
BS required, advanced degree preferred in electrical engineering, computer engineering computer science or related technical field from a top university or engineering institution
This position is not eligible for visa sponsorship.
Compensation:
The base salary range for this role is $200,000 - $320,000. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.
Benefits:
Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here (https://www.teradyne.com/2026-benefit-information-for-us-employees/) to see details.
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Current openings may involve access to export controlled technology and may be subject to export licensing requirements prior to employment. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our on-line application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form. In addition, you may also contact the HR Service Center at 978-370-3041 or contact them at HR.Service.Center@teradyne.com for additional assistance. LitePoint, a Teradyne Company is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor.