Job Information
Cadence Design Systems, Inc. Design Engineer II (Middle-end) in Nanjing, China
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description: Digital Design Engineer (Middle-end)
Position Overview
We are seeking a highly motivated Digital Design Engineer (Middle-end) to join our IP development team. This role will be responsible for middle-end implementation and signoff activities across the full IP development cycle, including synthesis, DFT, STA, ECO, and signoff.
The ideal candidate will work closely with cross-functional teams to deliver high-quality IP solutions for advanced technology programs. In addition to core engineering execution, this role is expected to contribute to AI-assisted design methodologies, flow automation, and productivity improvement initiatives to enhance design quality and development efficiency.
Key Responsibilities
Drive middle-end design activities including synthesis, DFT, STA, ECO, and signoff for IP development projects.
Support implementation and signoff work for advanced IP programs, including eUSB2v2 and UCIe AP/SP developments across multiple technology nodes.
Perform timing analysis and closure across different modes and corners, and support efficient ECO convergence.
Collaborate with front-end design, verification, physical design, DFT, and other cross-functional teams to ensure smooth project execution.
Develop, maintain, and optimize design flows, checks, and automation to improve QoR, robustness, and execution efficiency.
Participate in signoff quality review and issue resolution to ensure tapeout readiness.
Explore and apply AI/LLM-assisted methodologies to improve debug efficiency, workflow automation, and engineering productivity.
Identify opportunities to enhance the end-to-end IP development process through scripting, intelligent automation, and methodology improvement.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
Solid understanding of digital IC design and development flow.
Hands-on experience in one or more of the following areas: digital design, synthesis, DFT, STA, ECO, and signoff.
Familiarity with mainstream EDA tools and digital design/middle-end/signoff methodologies.
Experience with scripting and automation, such as Tcl, Python, Perl, or Shell, is strongly preferred.
Strong interest in applying AI technologies to semiconductor design workflows.
Strong analytical and problem-solving skills with attention to detail.
Good communication and teamwork skills, with the ability to work effectively across functions in a fast-paced development environment.
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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.