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Texas Instruments Resolution Enhancement Techniques Process Development Engineer in Dallas, Texas
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A Process Development Engineer is responsible for the development, characterization and optimization of MEMS resonator devices to meet the requirements for volume production as part of the analog technology development team. The ideal candidate will be a technical leader in the area of resonators and oscillators driving the characterization and optimization of the device and process to insure robustness, reliability, and manufacturability meeting all electrical device performance targets.
As a Resolution Enhancement Techniques (RET) modeling engineer, you'll create and optimize OPC models for Texas Instruments’ most advanced technology nodes. Models will include both lithography and etch-based models. Responsibilities will include, but are not limited to:
Partnering with design, process engineering and process integration teams to define design shapes needed for building accurate models.
Designing parameterized mask layouts needed for model building inputs.
Investigating and implementing ML and AI methods for improving model accuracy and runtime.
Implementing advanced optimization techniques.
Working with process engineering and process integration teams on wafer verification to validate model quality.
Working with OPC verification engineers to improve the accuracy of post-OPC verification models. These include but are not limited to weak image, assist feature printing, and resist top-loss models.
Why TI?
Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.
We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI (https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/pages/4012)
Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us.
About Texas Instruments
Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com .
Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws.
If you are interested in this position, please apply to this requisition.
Minimum requirements:
Masters in Electrical Engineering, Physics, Computer Science, Chemistry or related degree.
8 + years experience in OPC modeling in advanced node lithography.
Expertise in selecting and optimizing the features needed for properly sampling design spaces for building accurate models.
Expertise in developing test requirements to validate OPC modeling solutions.
Strong knowledge/understanding of advanced lithography simulation and RET techniques used in semiconductor manufacturing and process development.
Preferred qualifications:
Ability to lead and drive advanced processes associated with double patterning techniques in 22 nm node development.
Expertise in Synopsys ProGen modeling software.
Demonstrated knowledge of OPC verification software packages such as ORC, LMC+, or PLRC.
Knowledge of critical care-abouts for 28 and 22 nm node processing.
Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout execution using test pattern generators and use of layout software such as Cadence Virtuoso or KLayout.
Programming experience in Unix environment.
Understanding of OPC pattern validation methodologies and process window assessment techniques like KLA’s Photolithography Wafer Qualification (PWQ).
Demonstrated strong analytical and problem solving skills.
Strong verbal and written communication skills.
ECL/GTC Required: Yes