Job Information
onsemi Sr Principal ASIC / RTL Design Engineer in Brno, Czech Republic
Job Summary
We are seeking a skilled and motivated Senior Digital IC Design Engineer with over 5 years of experience in digital design and proven expertise in memory IP integration (SRAM, ROM, EEPROM, OTP/NVM). The candidate will play a key role in the development, integration, and verification of memory subsystems in advanced SoC platforms.
Key Responsibilities
Own and drive the integration of memory IPs into larger digital subsystems and SoC platforms.
Collaborate with memory IP teams to understand interface requirements, timing constraints, and test features.
Perform RTL design, lint, CDC, and synthesis for digital logic blocks interacting with embedded memories.
Define and execute design verification plans in coordination with the verification team.
Interface with physical design and validation teams to ensure successful implementation and bring-up.
Support post-silicon debug for memory interface-related issues.
Contribute to technical reviews, architecture discussions, and documentation of design flows
#LI-VS1
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
https://www.onsemi.com/careers/career-benefits
We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.