Job Information
Intel Senior IP Logic Design Engineer in Boxborough, Massachusetts
Job Details:
Job Description:
Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision.
Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet.
Life at Intel: https://jobs.intel.com/en/life-at-intel
The ideal candidate will develop the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.
Responsibilities include but are not limited to:
Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.
Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs.
Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation.
Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems.
Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases.
Mentor junior engineers and contribute to technical reviews and design documentation.
Stay updated with emerging technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.
Minimum Qualifications:
Education : MS/PhD in Electrical Engineering, Computer Engineering, or related field.
Experience :
10+ years in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding and at least one or more of the following:
Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI).
Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures).
Proven RTL coding experience in Verilog or SystemVerilog.
Proficiency in simulation tools for performance modeling and analysis.
Familiarity with physical design implications of memory fabric architectures (timing, power, area).
Experience with EDA tools for synthesis, linting, and static timing analysis.
Preferred Qualifications:
Hands-on experience with high-bandwidth memory (HBM), DDR, or other advanced memory technologies.
Background in AI/ML accelerator or data center SoC design.
Knowledge of scripting languages like Python or TCL for workflow automation.
Experience with software-hardware co-design for end-to-end system optimization.
Take the first step towards an impactful career at Intel by applying today. Let your passion for innovation and learning propel you into a future of limitless possibilities. Apply now and take the first step in your journey with Intel.
Interview Tips: https://www.intel.com/content/www/us/en/jobs/hiring.html
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, Massachusetts, Beaver Brook
Business group:
At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003) .
Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.